LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY CLKGEN IS
PORT(CLK: IN STD_LOGIC;
     NEWCLK: OUT STD_LOGIC);
END ENTITY CLKGEN;
ARCHITECTURE ART OF CLKGEN IS
--SIGNAL CNT: INTEGER RANGE 0 TO 10#49999999#;
SIGNAL CNT: INTEGER RANGE 0 TO 10#1#;
BEGIN
 PROCESS(CLK) IS
 BEGIN
 IF CLK'EVENT AND CLK='1' THEN
   --IF CNT=10#49999999# THEN CNT<=0;
   IF CNT=10#1# THEN CNT<=0;
   ELSE CNT<=CNT+1;
  END IF;
 END IF;
END PROCESS;
PROCESS(CNT) IS
   BEGIN
   --IF CNT=10#49999999# THEN NEWCLK<='1';
	 IF CNT=10#1# THEN NEWCLK<='1';
      ELSE
        NEWCLK<='0';
    END IF;
  END PROCESS;
 END ARCHITECTURE ART;

2.2 REG32B的VHDL源程序及分析

锁存器的工作原理就是将前一次测评的结果进行保存，并且传输到动态显示端，由于要将前一次测评结果清零所以锁存器的效果能够防止硬件不稳定的现象。

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY REG32B IS
  PORT(LOAD:IN STD_LOGIC;    --为1时候代表锁存器工作
       DIN:IN STD_LOGIC_VECTOR(31 DOWNTO 0);  --DIN是计数结果
		 DOUT:OUT STD_LOGIC_VECTOR(31 DOWNTO 0)); 
END ENTITY REG32B;
ARCHITECTURE ART OF REG32B IS
  BEGIN
	PROCESS(LOAD,DIN)IS
	 BEGIN
	  IF(LOAD'EVENT AND LOAD='1')THEN
		 DOUT<=DIN;
	  END IF;
	END PROCESS;
END ARCHITECTURE ART;

2.3 TESTCTL的VHDL源程序及分析

由于是多次测评，所以需要对程序进行一个整体的控制，测评控制模块非常重要，控制计数器何时工作，控制锁存器何时工作，对测评结果何时清零。

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY TESTCTL IS
--其中clk信号由分配器产生
   PORT(CLK:     IN STD_LOGIC;
	     TSTEN:   OUT STD_LOGIC; --输出时钟信号，用于控制计数器
		  CLR_CNT: OUT STD_LOGIC;  --清零信号，用于清除计数器数据
		  LOAD:    OUT STD_LOGIC); --用于发送给寄存器用于存储数据，其中电平波形于TSTEN相反
END ENTITY TESTCTL;
ARCHITECTURE ART OF TESTCTL IS
 SIGNAL DIV2CLK : STD_LOGIC;  --2分频时钟信号
 BEGIN
  PROCESS(CLK)  IS
   BEGIN
	 IF CLK'EVENT AND CLK='1' THEN
	 DIV2CLK<= NOT DIV2CLK;   --进行一个翻转
	 END IF;
   END PROCESS;
 PROCESS(CLK,DIV2CLK)  IS
	BEGIN
	 IF CLK='0'AND DIV2CLK='0' THEN
	   CLR_CNT<='1';
	  ELSE CLR_CNT <='0';
	 END IF;
  END PROCESS;
	LOAD<=NOT DIV2CLK;
	TSTEN <= DIV2CLK;
END ARCHITECTURE ART;

2.4 FREQ的VHDL源程序及分析

这是数字频率计的顶层文件，利用元件例化语句，将各模块进行一个连接。

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL; --六号口为被测频率口，8号口为动态扫描的端口
ENTITY FREQ IS
  PORT(FSIN:IN STD_LOGIC;
       CLK:IN STD_LOGIC;
		 CLK2:IN STD_LOGIC;
		 DOUT:BUFFER STD_LOGIC_VECTOR(31 DOWNTO 0);
		 COM:OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
		 SEG:OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END ENTITY FREQ;
ARCHITECTURE ART OF FREQ IS
  COMPONENT CNT10 IS
  PORT(CLK:IN STD_LOGIC;
       CLR:IN STD_LOGIC;
		 ENA:IN STD_LOGIC;
		 CQ:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
		 CO:OUT STD_LOGIC);
  END COMPONENT CNT10;
  COMPONENT REG32B IS
  PORT(LOAD:IN STD_LOGIC;
       DIN:IN STD_LOGIC_VECTOR(31 DOWNTO 0);
		 DOUT:OUT STD_LOGIC_VECTOR(31 DOWNTO 0)); 
  END COMPONENT REG32B;
  COMPONENT TESTCTL IS
  PORT(CLK:IN STD_LOGIC;
       TSTEN:OUT STD_LOGIC;
		 CLR_CNT:OUT STD_LOGIC;
		 LOAD:OUT STD_LOGIC);
  END COMPONENT TESTCTL;
  COMPONENT CLKGEN IS
PORT(CLK: IN STD_LOGIC;
     NEWCLK: OUT STD_LOGIC);
END COMPONENT CLKGEN;
  COMPONENT CTRLS IS
  PORT(CLK:IN STD_LOGIC;
       SEL:OUT STD_LOGIC_VECTOR(2 DOWNTO 0));
  END COMPONENT CTRLS;
  COMPONENT DISPLAY IS
  PORT(SEL:IN STD_LOGIC_VECTOR(2 DOWNTO 0);
       DATAIN:IN STD_LOGIC_VECTOR(31 DOWNTO 0);
		 COM:OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
		 SEG:OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
  END COMPONENT DISPLAY;
  SIGNAL SD:STD_LOGIC_VECTOR(31 DOWNTO 0);
  --SIGNAL DOUT:STD_LOGIC_VECTOR(31 DOWNTO 0); 
  SIGNAL S0,S1,S2,S3,S4,S5,S6,S7,S8,SC,SE,SL:STD_LOGIC;
  SIGNAL S9:STD_LOGIC_VECTOR(2 DOWNTO 0);
  BEGIN
  U0:CLKGEN PORT MAP(CLK=>CLK,NEWCLK=>S0);
  U1:TESTCTL PORT MAP(CLK=>S0,TSTEN=>SE,CLR_CNT=>SC,LOAD=>SL);
  U2:CNT10 PORT MAP(FSIN,SC,SE,SD(3 DOWNTO 0),S1);
  U3:CNT10 PORT MAP(S1,SC,SE,SD(7 DOWNTO 4),S2);
  U4:CNT10 PORT MAP(S2,SC,SE,SD(11 DOWNTO 8),S3);
  U5:CNT10 PORT MAP(S3,SC,SE,SD(15 DOWNTO 12),S4);
  U6:CNT10 PORT MAP(S4,SC,SE,SD(19 DOWNTO 16),S5);
  U7:CNT10 PORT MAP(S5,SC,SE,SD(23 DOWNTO 20),S6);
  U8:CNT10 PORT MAP(S6,SC,SE,SD(27 DOWNTO 24),S7);
  U9:CNT10 PORT MAP(S7,SC,SE,SD(31 DOWNTO 28),S8);
  U10:REG32B PORT MAP(SL,SD(31 DOWNTO 0),DOUT);
  U11:CTRLS PORT MAP(CLK2,S9);
  U12:DISPLAY PORT MAP(S9,DOUT,COM,SEG);
END ARCHITECTURE ART;